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Simple chips to "Emulate" 
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Joined: Sat 15 Aug 2009, 07:35:02

Posts: 77
Post Simple chips to "Emulate"
So I finally am getting a Papilio Pro* first I intend to learn to use it, but there isn't too much harm in planning ahead.
I was thinking about using the Papilio as a drop in replacement for simple chips to test what I can do initially, using and to easily test if my designs work or not, so I wish to ask for non to complex chips which is either ubiquitous or is available either in the Super Nintendo or the Amiga 500, preferably the Amiga since that uses sockets for most chips, that doesn't have more than 48 data lines as that is the amount I will have available on the Papilio, info on the chip would be nice too. Other than that, go nuts I guess.

*http://papilio.gadgetfactory.net/index.php?n=Papilio.PapilioPro

/Zorbeltuss

Sat 26 Oct 2013, 13:54:30

Joined: Tue 21 Feb 2012, 05:42:15

Posts: 2564
Post Re: Simple chips to "Emulate"
There was a talk posted here about the inner workings of the 6502. I found it to be an intriguing and yet very simplistic processor; perhaps it would make a good target.

6502 and 6502 variants are widely found in all kinds of old computers and video game systems. The NES uses the 2A03, which is based on the 6502. Similarly, the SNES uses a derivative of 65C816, which is in turn a (16-bit) derivative of the 6502. The 65C816 was used in the Apple IIGS.

Of course, I have no idea if it's a good idea to jump into FPGAs by implementing a real life processor. I have never used an FPGA (although I really am interested by them - one of those things I simply must play with some day) but perhaps simple hobby CPUs are a better start, assuming some exist.

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Sat 26 Oct 2013, 15:05:27

Joined: Sat 15 Aug 2009, 07:35:02

Posts: 77
Post Re: Simple chips to "Emulate"
The 6502 is a very interesting processor, just need to keep myself in check to not do any "improvements" on it, apart from that, there are many derivates, true but the Nintendo ones not only adds to the 6502 but removes as well and thus I'm not terribly keen on making them, at least until I've made a working 6502, maybe if I could find a c64 in a saveable condition, yea, if I find one, I'll give it a go.

Edit: Yeah, probably not the best idea to begin with, that's why I won't, but planning keeps me going when the going get tough, because then I have something interesting to look forward to. There are also many simple special chips in that era that aren't processors, like the Nintendo CIC but that would be rather heinous to implement, as it mostly hinders you from playing real games.

Edit: Ok if I do a 6502 I will probably have an interrupt or exception when the state gets killed by a kil undocumented opcode, other than that, I do not want to make to many changes initially.

/Zorbeltuss

Sat 26 Oct 2013, 15:13:10
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Joined: Tue 02 Nov 2010, 01:00:37

Posts: 181
Post Re: Simple chips to "Emulate"
Whoa, whoa, whoa, whoa!

So you are just starting out with FPGAs, and the whole toolflow and workflow are new to you? Then I suggest you start off way smaller than that.

First, get familiar with the basics of the tools. Decide whether you want to start with Verilog or VHDL. ISE is a pretty crappy tool. Clean your project often.
Then, make some small things. A blinking LED, a PWM, a shift register.

After you made and tested these, look at the final routed result. Make sure that for instance your shift register will actually use a hardware primitive shift register and not use LUT logic and DFFs. Find out why your description would cause your tool to infer LUTs and DFFs when you want SRLs. Change that.

If you plan to do serious I/O business, look at what features your IOBs offer. Look at how your hardware description affects placement of DFFs into IOBs. Understand all of it.

Next, brush up on constraints and look at their effects. How does routing change when you set the minimum period of your clock to 2.5 ns; 5 ns etc.

Read some whitepapers on synchronous reset methodology and local reset methodology, their pros and cons and why everybody should use it.

After you have done that, you may possibly, remotely think about doing a CPU and actually knowing what you're doing. You will find many courses -- both online and offline -- that just brush over these things to get the users to reach their immediate goals. However, if you want to move on to some serious projects with zilch knowledge of all of the above, you will pretty much hit a road block and quickly and easily get frustrated.

cYa,

Tauwasser

Sun 27 Oct 2013, 23:21:19

Joined: Sat 15 Aug 2009, 07:35:02

Posts: 77
Post Re: Simple chips to "Emulate"
Tauwasser wrote:
So you are just starting out with FPGAs, and the whole toolflow and workflow are new to you? Then I suggest you start off way smaller than that.


First, get familiar with the basics of the tools. Decide whether you want to start with Verilog or VHDL. ISE is a pretty crappy tool. Clean your project often.
Then, make some small things. A blinking LED, a PWM, a shift register.


Probably should have been clearer than I was about this, I have read a book on VHDL an that is what I intend to use, I will get the logic start megawing which also contains a book on VHDL.
I don't really Intend to start big, but I want something to look forward too and something should be testable by drop in replacement.
Also as I haven't used it, how is ISE a crappy tool and are there ways to circumvent that?

Tauwasser wrote:
After you made and tested these, look at the final routed result. Make sure that for instance your shift register will actually use a hardware primitive shift register and not use LUT logic and DFFs. Find out why your description would cause your tool to infer LUTs and DFFs when you want SRLs. Change that.

If you plan to do serious I/O business, look at what features your IOBs offer. Look at how your hardware description affects placement of DFFs into IOBs. Understand all of it.

Next, brush up on constraints and look at their effects. How does routing change when you set the minimum period of your clock to 2.5 ns; 5 ns etc.

Read some whitepapers on synchronous reset methodology and local reset methodology, their pros and cons and why everybody should use it.

Most of these things are covered by the book I've read, although that book was in swedish so I had to look up most of the terms you mention to actually see that, next book is going to be in english though. So I hope it covers that too.

Tauwasser wrote:
After you have done that, you may possibly, remotely think about doing a CPU and actually knowing what you're doing. You will find many courses -- both online and offline -- that just brush over these things to get the users to reach their immediate goals. However, if you want to move on to some serious projects with zilch knowledge of all of the above, you will pretty much hit a road block and quickly and easily get frustrated.

cYa,

Tauwasser

I have done designs for CPUs in logic gates before and I have implemented a design for a MISC set computer (not terribly useful I know but it is something) in java, before.

Lastly I was hoping for simpler suggestions in the thread, like if anyone have data on how the superCIC works or similar, I also have a project int his manner I've already desided on, when I feel like it might be possible, I'm going to try making a replacement RF modulator for my amiga, which may output RF or just take the RBG and rework it to composite, as I haven't seen much in the way of explaining how RF works.

/Zorbeltuss who just don't want to get stuck on counters and shift registers and not have a plan for the future and drop the whole project because the lack of anything fun in the plan ahead.

Mon 28 Oct 2013, 03:36:42
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Joined: Tue 02 Nov 2010, 01:00:37

Posts: 181
Post Re: Simple chips to "Emulate"
Zorbeltuss wrote:
Also as I haven't used it, how is ISE a crappy tool and are there ways to circumvent that?


It will often get confused about your files, only compile half your design and use previously synthesized modules although files have changed. Pretty much clean your project every so often and look at and understand all messages. It can be pretty obvious when you change a file, re-synthesize and the messages contain old assignments to generics etc. But it's harder to catch on some other occasions. Also, avoid the internal text editor like the devil avoids holy water... Instead, use anything else. Use notepad.exe if you have to. It's still better.

Zorbeltuss wrote:
Most of these things are covered by the book I've read, although that book was in swedish so I had to look up most of the terms you mention to actually see that, next book is going to be in english though. So I hope it covers that too.


Trust me when I dare say that most books only cover a very limited repertoire of a) the languages themselves b) the tools c) constrains d) actual synthesis. They will cover lots of easy-to-do code that can be simulated in some crappy free simulator and will work, yet fail synthesis. Beware.

Zorbeltuss wrote:
I have done designs for CPUs in logic gates before and I have implemented a design for a MISC set computer (not terribly useful I know but it is something) in java, before.


Well, that's a good start. You might want to take a look at some open source CPUs out there. For instance some AVR8 reimplementations, or directly use Xilinx' EDK if you can - so you can design your own RISC CPU and make sure it works by having something workable at your fingertips.

Zorbeltuss wrote:
/Zorbeltuss who just don't want to get stuck on counters and shift registers and not have a plan for the future and drop the whole project because the lack of anything fun in the plan ahead.


IMHO having big plans doesn't exempt you from doing the small stuff first and walking into possible problems there. You can plan ahead to make your own SNES game PCB with your own DSP that is implemented by you on the FGPA for example. Drop-in replacements will need some level shifter dangling somewhere (those incur propagation delays and skew) or you grill your Spartan 6.

Zorbeltuss wrote:
I'm going to try making a replacement RF modulator for my amiga, which may output RF or just take the RBG and rework it to composite, as I haven't seen much in the way of explaining how RF works.


What kind of DAC/ADC are you going to use for that adventure? Or does the Amiga output digital somewhere along the way where you can get easy access?

cYa,

Tauwasser

Sat 02 Nov 2013, 02:00:24

Joined: Sat 15 Aug 2009, 07:35:02

Posts: 77
Post Re: Simple chips to "Emulate"
Tauwasser wrote:
Zorbeltuss wrote:
/Zorbeltuss who just don't want to get stuck on counters and shift registers and not have a plan for the future and drop the whole project because the lack of anything fun in the plan ahead.


IMHO having big plans doesn't exempt you from doing the small stuff first and walking into possible problems there. You can plan ahead to make your own SNES game PCB with your own DSP that is implemented by you on the FGPA for example. Drop-in replacements will need some level shifter dangling somewhere (those incur propagation delays and skew) or you grill your Spartan 6.

I intend to do the the small things first, but without further plans the papilio is probably quite prone to collect dust. About the level shifter, yes I will definitely need that, however at speeds below 10 Mhz, will the delays really be much of a problem?


Tauwasser wrote:
Zorbeltuss wrote:
I'm going to try making a replacement RF modulator for my amiga, which may output RF or just take the RBG and rework it to composite, as I haven't seen much in the way of explaining how RF works.


What kind of DAC/ADC are you going to use for that adventure? Or does the Amiga output digital somewhere along the way where you can get easy access?

cYa,

Tauwasser

Had to look it up, 'cause my memory failed me, but yes there is digital out on the amiga 500, however only video and only 16 colors out of 4096 (cga style), so I'm probably not going to use that, for adc I will try to find something with a moderatly overkill frequency overkill so I won't have to mess around to much, 4 bits per channel would probably be enough, but it depends on what I can find, for the audio which is 8 bit I'd probably not need more than that, although to avoid sampling errors I might overkill a bit on that too, for dac I'll probably just get high accuracy resistors to do a resistor ladder, although the papilio seems to be capable of of doing delta-sigma and that might be another way to go (or maybe both to have two outputs to compare quality).

/Zorbeltuss

Sun 03 Nov 2013, 22:06:24
User avatar

Joined: Tue 02 Nov 2010, 01:00:37

Posts: 181
Post Re: Simple chips to "Emulate"
Zorbeltuss wrote:
About the level shifter, yes I will definitely need that, however at speeds below 10 Mhz, will the delays really be much of a problem?


Well, since many circuits on there -- especially on cartridges -- are combinational in nature, you will have to synchronize the inputs to whatever clock you use on the inside. Since you would obviously want high frequencies, you will have to keep in mind that signals might come in delayed, skewed etc. For instance, if you use 100 MHz provided by a DCM from the 32 MHz OSC input, then you would be at 10 ns per clock cycle already. Level shifter delays are typically of the same magnitude, see for instance the fairly common TXB0108.

Zorbeltuss wrote:
for adc I will try to find something with a moderatly overkill frequency overkill


Oh, ok??

Zorbeltuss wrote:
for dac I'll probably just get high accuracy resistors to do a resistor ladder, although the papilio seems to be capable of of doing delta-sigma and that might be another way to go (or maybe both to have two outputs to compare quality).


Well, you should at least run a spice simulation for such resistor ladders. IMHO settling time is very slow for those, which might or might not become an issue for you.

cYa,

Tauwasser

Sun 03 Nov 2013, 23:26:25

Joined: Sat 15 Aug 2009, 07:35:02

Posts: 77
Post Re: Simple chips to "Emulate"
Tauwasser wrote:
Zorbeltuss wrote:
About the level shifter, yes I will definitely need that, however at speeds below 10 Mhz, will the delays really be much of a problem?


Well, since many circuits on there -- especially on cartridges -- are combinational in nature, you will have to synchronize the inputs to whatever clock you use on the inside. Since you would obviously want high frequencies, you will have to keep in mind that signals might come in delayed, skewed etc. For instance, if you use 100 MHz provided by a DCM from the 32 MHz OSC input, then you would be at 10 ns per clock cycle already. Level shifter delays are typically of the same magnitude, see for instance the fairly common TXB0108.

Well that may be a problem for the super cic, I don't know what kind of tolerances the snes has got, the amiga however is hardware hacked beyond anything else and it can take atleast 70ns on all components, and most components can take off-cycle inputs.

Tauwasser wrote:
Zorbeltuss wrote:
for adc I will try to find something with a moderatly overkill frequency overkill


Oh, ok??

As sampling might be taken on the edges, one might be getting bad values, to avoid that one can take 4 samples per change to get it right, after that I will want to take 6 to 8 samples instead of 4 (as in overkill). That means an ADC that is capable of 50 to 70 Mhz roughly.
Tauwasser wrote:
Zorbeltuss wrote:
for dac I'll probably just get high accuracy resistors to do a resistor ladder, although the papilio seems to be capable of of doing delta-sigma and that might be another way to go (or maybe both to have two outputs to compare quality).


Well, you should at least run a spice simulation for such resistor ladders. IMHO settling time is very slow for those, which might or might not become an issue for you.

cYa,

Tauwasser

Will do, that might change whether I put out composite or RF, composite will work though, as that has already been done with resistor ladder on the papilio (a really quite nifty master system clone or what one can call it).

/Zorbeltuss who will need to find his amiga 500 hardware guide with associated motherboard blueprints before any mad work on it

Mon 04 Nov 2013, 00:56:44

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